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Re: Anna University Question Bank for CSE 7th SEM
The Anna University is invited candidates for B.Tech CSE course. Also the Anna University is provides question bank for B.Tech students. The Anna University was established on 4th September, 1978 as a unitary type of University. It offers higher education in Engineering, Technology, Architecture and Applied Sciences relevant to the current and projected needs of the society. Besides promoting research and disseminating knowledge gained therefrom, it fosters cooperation between the academic and industrial communities. Get question paper from Anna University in Question Bank For CSE 7th Sem: Anna University Question Bank For Cse 7th Sem: CS 182/Cs 9152 & Digital Principles And System Design Time: 3 Hours Answer ALL Questions Max. Marks 100 PART-A (10 2 = 20 Marks) 1. State distributive law and associative law. 2. Obtain 2's complement of 01110110 3. Draw the full adder circuit using two half adders. 4. Draw the logic diagram of carry look ahead generator 5. What is a decoder? 6. Draw the diagram of three state buffer. 7. Draw the characteristic table of JK and T flip flops. 8. Draw the logic diagram of SR latch. 9. What is a fundamental mode of operation? 10. Draw the excitation table of SR latch using NAND gates. Part - B(5 1 6 = 80 marks) 11. Minimize F(A,B,C,D) = (0,5,7,8,9,10,11,14,15) using QM method (16) 12. a) Convert the following into other canonical forms (16) F(x,y,z) = 1(0,2,3,5,7,9,11,15) F(A,B,C,D) = TT(3,4,6,7,8,9,1 1,12,13) OR b) Explain how the binary code is converted to gray code. (16) 13. a) i) Explain Priority encoder (8) ii) Write the HDL gate level description of the above circuit (8) OR b) i) Draw the 4 bit magnitude comparator and explain. (8) ii) Draw block diagram of BCD adder and explain. (8) 14. a) Design a mod 6 synchronous counters using JK flip flops. (16) OR b) i) Draw the diagram of universal shift register (6) ii) Draw the diagram of 4 bit binary counter with parallel load and explain (10) 15. a) An asynchronous sequential circuit is described by the excitation function Y=XiX2'+(x 1+x 2')y and the output function z=y. (16) i) Draw the logic diagram of the circuit ii) Derive the transition table and output map iii) Obtain a two-state flow table iv) Describe in words the behavior of the circuit OR i) Explain race free assignment with appropriate example. ii) Explain static 0 and static 1 hazard in combinational circuits |
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