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  #1  
Old 4th April 2013, 05:34 PM
Goutamm
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Default ECIL Sample Papers Download

I am going to participate in ECIL Graduate Engineer Trainee Get exam Will you give me ECIL Graduate Engineer Trainee Get Sample Papers.
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  #2  
Old 6th April 2013, 05:35 PM
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Join Date: May 2012
Default Re: ECIL Sample Papers Download

Here i am provide ECIL Graduate Engineer Trainee Get Sample Papers.

1.The current I in the given network.
a) 1A
b) 3A
c) 5A
d) 7A

2.For the Delta‐ Wye transformation in given figure, the value of the resistance R is.
a) 1/3 ohms
b) 2/3 ohms
c) 3/2 ohms
d) 3 ohms

3.In the given network, the Thevenin’s equivalent as seen by the load resistance Rl is
a) V=10 V, R= 2ohms
b) V=10V, R=3 ohms
c) V=15V, R= 2ohms
d) V=15V, R=3 ohms

4.The current I in a series R‐L circuit with R=10 ohms and L=20mH is given by i=2sin500t A. If v is the voltage across the R‐L combination then i
a) lags v by 45 degree
b) is in‐phase with v
c) leads v by 45
d) lags v by 90

5.In thr given network, the mesh current I and the input impedance seen by the 50 V source, respectively, are
a) 125/13 A and 11/8 ohms
b) 150/13 A and 13/8 ohms
c) 150/13 A and 11/8 ohms
d) 125/13 A and 13/8 ohms

6.A voltage sourcehaving a source impedance Z = R + jX can deliver maximum Average power to a load impedance Z, when
a) Z = R + jX
b) Z = R
c) Z = jX
d) Z = R –jX

7.In the given circuit, the switch S is closed at t=0. Assuming that there is no initial Charge in the capacitor, the current i(t) for t>0 is
a) V/R e^ (‐2t/RC)
b) V/R e^ (‐t/RC)
c) V/2R e^ (‐2t/RC)
d) V/2R e^ (‐t/RC)

8.For the circuit in given figure, if e(t) is a ramp signal, the steady state value of the Output voltage v(t) is
a) 0
b) LC
c) R/L
d) RC

9.For the series RLC circuit in given figure, if w=1000 rad/sec, then the current I (in Amperes) is
a) 2 ∟‐15
b) 2 ∟15
c) √2∟‐15
d) √2∟15

10.The Y‐parameter matrix (mA/V) of the two‐port given network is
a) [2 ‐1 ‐1 2]
b) [2 1 ‐1 2]
c) [1 ‐2 ‐1 2]
d) [2 1 1 2]

For detail of question paper here attachment:-
Attached Files
File Type: pdf ECIL GET exam paper.pdf (365.0 KB, 112 views)
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  #3  
Old 8th April 2018, 07:12 PM
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Default Re: ECIL Sample Papers Download

Hello sir, here I came for to get download sample papers for Electronic Corporation of India Limited. Will you please provide me Electronic Corporation of India Limited sample papers?
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  #4  
Old 8th April 2018, 07:15 PM
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Join Date: Mar 2013
Default Re: ECIL Sample Papers Download

The Electronic Corporation of India Limited was released Graduate Engineer Trainee Recruitment Notification to fill up vacancies.

Applied intenders can refer the ECIL GET Exam Sample Papers once before taking the exam.

The individuals only who have proper preparation will be selected for the next round.

Paper pattern:

Type of Exam Names of the Subjects Duration of the Test
Objective Type (Computer-Based Test Technical Questions from Degree related Syllabus from Particular Disciplines 1 Hr 30 mins


ECIL CECE question paper






ECIL CECE question paper:

1.The current I in the given network.
a) 1A
b) 3A
c) 5A
d) 7A

2.For the Delta‐ Wye transformation in given figure, the value of the resistance R is.
a) 1/3 ohms
b) 2/3 ohms
c) 3/2 ohms
d) 3 ohms

3.In the given network, the Thevenins equivalent as seen by the load resistance Rl is
a) V=10 V, R= 2ohms
b) V=10V, R=3 ohms
c) V=15V, R= 2ohms
d) V=15V, R=3 ohms

4.The current I in a series R‐L circuit with R=10 ohms and L=20mH is given by i=2sin500t
A. If v is the voltage across the R‐L combination then i
a) lags v by 45 degree
b) is in‐phase with v
c) leads v by 45
d) lags v by 90

5.In thr given network, the mesh current I and the input impedance seen by the 50 V source,
respectively, are
a) 125/13 A and 11/8 ohms
b) 150/13 A and 13/8 ohms
c) 150/13 A and 11/8 ohms
d) 125/13 A and 13/8 ohms

6.A voltage sourcehaving a source impedance Z = R + jX can deliver maximum Average
power to a load impedance Z, when
a) Z = R + jX
b) Z = R
c) Z = jX
d) Z = R jX

7.In the given circuit, the switch S is closed at t=0. Assuming that there is no initial Charge in
the capacitor, the current i(t) for t>0 is
a) V/R e^ (‐2t/RC)
b) V/R e^ (‐t/RC)
c) V/2R e^ (‐2t/RC)
d) V/2R e^ (‐t/RC)


8.For the circuit in given figure, if e(t) is a ramp signal, the steady state value of the Output
voltage v(t) is
a) 0
b) LC
c) R/L
d) RC

Here Im attaching PDF for ECIL CECE question paper:
Attached Files
File Type: pdf ECIL CECE question paper.pdf (572.2 KB, 30 views)
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