Sathyabama Institute of Science and Technology BE ECE SECA1602 Programming in HDL Syllabus
 

Sathyabama Institute of Science and Technology BE ECE SECA1602 Programming in HDL Syllabus

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY

SECA1602 PROGRAMMING IN HDL

UNIT 1 BASIC CONCEPTS IN VHDL 9 Hrs.
Digital system design process - Hardware simulation - Introduction to VHDL - Language elements of VHDL - Data objects -
Data types - Operators - Signal assignments - Inertial delay mechanism - Transport delay mechanism - Variable
assignments - Concurrent and Sequential assignments- Delta delay.

UNIT 2 MODELING IN VHDL 9 Hrs.
Data flow modelling - Concurrent Signal Assignment statements - Structural modelling – Component declaration -
Component Instantiation – Behavioral modelling - Process statement - wait statement - Conditional and loop statements -
Generics and configurations - Examples for modelling.

UNIT 3 INTRODUCTION TO VERILOG HDL 9 Hrs.
Basic concepts - Levels for design description - Module - Delays - Language elements - Compiler directives - value set -
data types - Parameters - Expressions - Operands - operators in verilog HDL.

UNIT 4 STYLES OF MODELING 9 Hrs.
Gate level modelling -Primitive Gates- Multiple input and multiple output gates - User Defined Primitives - Combination UDP
- Sequential UDP- Data flow modelling - Behavioral modelling - procedural constructs – procedural assignments -
conditional and loop statements - Structural Modelling - Examples for modelling.

UNIT 5 FEATURES IN VERILOG HDL 9 Hrs.
Synthesis of sequential circuits, Study of synchronous and asynchronous sequential circuits, Flip flops, Shift Registers,
Counters and their design using Verilog-Tasks- Functions -systems tasks and functions - Verification - Modeling a test
bench - timing and delays - Switch level modeling - state machine modeling - Moore FSM - Melay FSM - Design of
memories Design of microcontroller CPUs.
Max. 45 Hrs.

COURSE OUTCOMES
On completion of the course, student will be able to
CO1 - Identify any design requirements to solve problems in various domains.
CO2 - Analyse the sequential logic both in synchronous and Asynchronous modes for various complex logic and switching
devices and validate the outputs.
CO3 - Conceptualize the system through design and modeling various architectures.
CO4 - Develop any design based upon the system requirements for solving real time problems.
CO5 - Validation and verification of the system design.
CO6 - Design a test bench for any logic
.
TEXT / REFERENCE BOOKS
1. J.Bhaskar, “A VHDL Primer”, Prentice Hall of India Limited. 3rd Edition 2004.
2. Douglas L. Perry, "VHDL", McGraw Hill, 2002.
3. J.Bhaskar, “A Verilog HDL Primer”, Prentice Hall of India Limited. 3rd Edition 2004.
4. Stephen Brown, "Fundamental of Digital logic with VHDL Design", Tata McGraw Hill, 2008.
5. Michael D. Ciletti; “Advanced Digital Design with the Verilog HDL”; 2009, 1st Edition, 2010.

END SEMESTER EXAMINATION QUESTION PAPER PATTERN
Max. Marks: 100 Exam Duration: 3 Hrs.
PART A: 10 Questions of 2 marks each – No choice 20 Marks
PART B: 2 Questions from each unit of internal choice; each carrying 16 marks 80 Marks