Mumbai University BE E&TC Syllabus

Hi I am studying in the 7 sem E and TC branch of Mumbai university I want syllabus of the 7 semester for my branch please provide me soon its urgent?

[Saksham]

As you want to known about the syllabus of the Syllabus of the Bachelor of engineering E&TC 7 semester

Here I am providing the same to you

VLSI Design

1. Introductionto VLSI Evolution of logical complexity in ICs as afunction of time, VLSI design flow, Y-chartrepresentation, design hierarchy/design abstraction levels in digital circuits, concepts ofregularity, modularity and locality, Semi-custom& full custom devices

2. Physics ofMOSFET
MOS capacitor, energy band diagrams, band bending, flat band voltage, threshold voltage calculation, threshold adjustment, MOSFET linear and saturated operation(GCA), OSFETcapacitance, channel length modulation. Types of scaling, functional limitations of scaling,short channel, narrow channel effects, hotelectron effects.

3.
Semiconductor manufacturing process
Wafer processing, mask generation, oxidation, epitaxy, ion implantation, diffusion, metallization, photolithography, process steps for NMOS & PMOS devices, CMOS inverters, latch-up inCMOS and its prevention. Process simulation using CAD tools Video of manufacturing processto be shown.

4.Design rules and layout Need of design rules, NMOS, PMOS and CMOS design rules and layouts. Design of NMOS and CMOS Inverter, NAND and NOR gates. Interlayer contacts, Butting and Buried contacts. Stick diagrams, layout of integrated circuits.
Realization of Boolean expressions in CMOS. Use of CAD tools for layout design and simulation.


5.MOS Inverters
MOS inverters - resistive load - NMOS load -pseudo NMOS (Qualitative) and CMOS inverters (quantitative) -calculation of noise margin, calculation of rise, fall and delay times for CMOS inverter, transistor sizing and power dissipation , series and parallel equivalency rules, equivalent inverter (numericals on noise margin calculations, timing calculations, power dissipation, equivalency expected)

6. Verilog Basic concepts, structural gate level, switch level, behavior and RTL modeling. Arithmetic Circuits in CMOS VLSI ñ carry look ahead adder, high speed adders, subtractors, decoders, multiplexer and multipliers. Sequential circuits implementation using verilog (Flip-Flop, registers and counters, state machines).

subject fillter design

1 Analog filters
Filter specifications, Introduction to Butterworth Chebyshev, design (Derivation of T.F.), Elliptical filters, Frequency Transformations Low pass, high pass and band pass active filter
realization, infinite gain single amplifier (LP,BP & HP) , positive and negative feedback infinite gain singleamplifier filters, high order filters.

2 Direct realization methods:
Active network elements for direct realization,inductance simulation frequency dependent negativeresistors, leapfrog realization techniques, primaryresonator block, switched capacitor filters.

3
IIR filter design
IIR filter design methodology, Design of Butterworth and Chebyshev filters using Impulse/step invariant method, matched Z Transform method, Bilinear transform Technique. Spectral transformationsFilter design by pole zero placements.

4 FIR filter : Analysis and design
Linear phase FIR filter and its types, FIR filter designusing windows and Frequency sampling method, Half Band FIR filter design.

5
Adaptive Filters:
Concept of adaptive filter ,MMSE criterion ,LMS andRLS algorithms ,Basic Weiner filter and itsapplications
6
Multirate Digital signal Processing
Concepts Decimation Interpolation ,sampling rate conversion by raional factor, polyphase structures ,multistage implementation ,applications like subband coding and Quadrature mirror filtering.