| 24th September 2020 11:50 AM | |
| Arvind Kumar | Sathyabama Institute of Science and Technology M.Tech - VLSI SECA7012 Algorithms and Sathyabama Institute of Science and Technology M.Tech - VLSI SECA7012 Algorithms and Architecture for Signal Processing ICs Syllabus SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SECA7012 ALGORITHMS AND ARCHITECTURE FOR SIGNAL PROCESSING ICs (For VLSI& AE) UNIT 1 ARCHITECTURES FOR DIGITAL SIGNAL-PROCESSORS 9 Hrs. Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Features for External Interfacing. UNIT 2 PROGRAMMABLE DIGITAL SIGNAL PROCESSORS 9 Hrs. Introduction, Commercial digital Signal-processing Devices, Data Addressing Modes of TMS32OC54xx.,Memory Space of TMS32OC54xx Processors, Program Control, Detail Study of TMS320C54X & 54xx Instructions and Programming, On-Chip peripherals, Interrupts of TMS32OC54XX Processors, Pipeline Operation of TMS32OC54xx Processor. UNIT 3 IMPLEMENTATION OF BASIC DSP ALGORITHMS 9 Hrs. Introduction, The Q-notation, FIR Filters, IIR Filters, Interpolation and Decimation Filters (one example in each case). An FFT Algorithm for DFT Computation, Overflow and Scaling, Bit-Reversed Index Generation & Implementation on the TMS32OC54xx. UNIT 4 INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO DSP DEVICES 9 Hrs. Introduction, Memory Space Organization, External Bus Interfacing Signals. Memory Interface, Parallel I/O Interface, Programmed I/O, Interrupts and I / O Direct Memory Access (DMA). UNIT 5 INTERFACING AND APPLICATIONS OF DSP PROCESSOR 9 Hrs. Introduction, Synchronous Serial Interface, A CODEC Interface Circuit. DSP Based Bio- telemetry Receiver, A Speech Processing System, An Image Processing System, Vetterbi Decoder, Nanospa architecture. Max. 45 Hrs. COURSE OUTCOMES On completion of the course, student will be able to CO1 - Understanding the basics of digital signal processors and its interfacing. CO2 - Developing the programming skills by facilitating a clear understanding on the instruction set of programmable digital signal processors. CO3 - Design, develop and implement of FIR ,FFR, interpolator , decimator, FFT,DFT using DSP. CO4:Comprehending the basic memory space organization ,interface and programme I/O, interrupts and I/O direct memory access. CO5 - Clear insight on the real time applications on the DSP processor example speech, image processing, Viterbi, nano spa architecture. CO6 - Investigate the feasibility of providing solutions to real time challenges in telemedicine , remote sensing by DSP. TEXT / REFERENCE BOOKS 1. Nagoor Khani, "Digital Signal Processing", TMG, 2012. 2. Ifeachor E.C., Jervis B.W., "Digital Signal Processing: A practical approach", Pearson Education, PHI/ 2002. 3. B.Venkataramani and M.Bhaskar, " Digital Signal Processors", TMH, 2002. 4. Peter Pirsch, Architectures for Digital Signal Processing", Publisher Wiley Publisher, 2015. END SEMESTER EXAMINATION QUESTION PAPER PATTERN Max. Marks: 100 Exam Duration: 3 Hrs. PART A: 5 Questions of 6 Marks each – No choice 30 Marks PART B: 2 Questions from each unit of internal choice, each carrying 14 Marks 70 Marks |
