12th November 2016 01:03 PM | |
shikha | Re: VHDL Syllabus VTU Visvesvaraya Technological University is a collegiate public state university in Karnataka State, India. It was established by the Government of Karnataka. VHDL Syllabus: Part A Unit-1 Introduction 7 hours VHDL description of combinational networks, Modeling flip-flops using VHDL, VHDL models for a multiplexer, Compilation and simulation of VHDL code, Modeling a sequential machine, Variables, Signals and constants, Arrays, VHDL operators, VHDL functions, VHDL procedures, Packages and libraries, VHDL model for a counter. Unit-2 Designing With Programmable Logic Devices 6 hours Read-only memories, Programmable logic arrays (PLAs), Programmable array logic (PLAs), Other sequential programmable logic devices (PLDs), Design of a keypad scanner. Unit-3 Design Of Networks For Arithmetic Operations 6 hours Design of a serial adder with accumulator, State graphs for control networks, Design of a binary multiplier, Multiplication of signed binary numbers, Design of a binary divider. Unit-4 Digital Design with SM Charts 7 hours State machine charts, Derivation of SM charts, Realization of SM charts. Implementation of the dice game, Alternative realization for SM charts using microprogramming, Linked state machines. Part B Unit-5 Designing With Programmable Gate Arrays And Complex Programmable Logic Devices 6 hours Xlinx 3000 series FPGAs, Designing with FPGAs, Xlinx 4000 series FPGAs, using a one-hot state assignment, Altera complex programmable logic devices (CPLDs), Altera FELX 10K series COLDs. Unit-6 Floating - Point Arithmetic 7 hours Representation of floating-point numbers, Floating-point multiplication, Other floating-point operations. Unit-7 Additional Topics In VHDL 7 hours Attributes, Transport and Inertial delays, Operator overloading, Multi-valued logic and signal resolution, IEEE-1164 standard logic, Generics, Generate statements, Synthesis of VHDL code, Synthesis examples, Files and Text IO. Unit-8 VHDL Models For Memories And Buses 6 hours Static RAM, A simplified 486 bus model, Interfacing memory to a microprocessor bus. VTU VHDL paper Contact: Visvesvaraya Technological University (VTU) Jnana Sangama, VTU Main Road, Machhe Belagavi, Karnataka 590018 Phone: 0831 249 8196 |
12th November 2016 12:33 PM | |
Unregistered | VHDL Syllabus VTU I am doing engineering degree from Visvesvaraya Technological University (VTU) searching for the syllabus. Can you provide me VHDL Syllabus of VTU so that I get to know list of subjects I will study in this also provide some sample VHDL papers so I know about level of questions? |