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Default Sathyabama Institute of Science and Technology M.E. - Applied Electronics SECA5111 Advanced Digital System Design Syllabus

Sathyabama Institute of Science and Technology M.E. - Applied Electronics SECA5111 Advanced Digital System Design Syllabus

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING

SECA5111 ADVANCED DIGITAL SYSTEM DESIGN
L T P Credits Total Marks
3 0 0 3 100

UNIT 1 INTRODUCTION TO COMBINATIONAL AND SEQUENTIAL LOGIC CIRCUITS 9 Hrs.
Combinational: Introduction; General Approach to Combinational Logic Design; Introduction to Digital Integrated Circuits;
Decoders; Encoders; Digital Multiplexers; Binary Comparators; Array Multipliers; Tristate Buffers. Sequential: Latches; Flip-
Flops; Counters-Ring counter and Johnson Counter.

UNIT 2 SYNCHRONOUS SEQUENTIAL NETWORKS 9 Hrs.
Structure and Operation of Synchronous Sequential Networks: Moore model, Mealy model-Analysis of Clocked
Synchronous Sequential Networks (CSSN); Transition equations, Transition tables, Excitation tables, State Tables, State
diagrams - Modelling of CSSN behaviour: Serial binary adder as a mealy and Moore network, Sequence recogniser.

UNIT 3 CSSN TABLE REDUCTION TECHNIQUES AND ASM 9 Hrs.
State Table Reduction–Implication Table for determining equivalent states of the table, Obtaining Equivalence Classes of
states, Constructing the minimum state table –State Assignment, Unused states Algorithmic state Machines–ASM Charts :
The state box , The decision box, Conditional output box, ASM blocks, ASM chart for mod n binary counter – relationship
between state diagram and ASM charts - ASM Chart for a sequence recogniser- ASM Chart for binary multiplier

UNIT 4 ASYNCHRONOUS SEQUENTIAL NETWORKS 9 Hrs.
Structure and Operation of Asynchronous Sequential Networks (Fundamental and Pulse Mode); Analysis of Asynchronous
Sequential Networks (ASN); Design of ASN; Primitive Flow Table; Flow Table Reduction; Races in ASC–Static and Dynamic
Hazards; Essential Hazards;

UNIT 5 PROGRAMMABLE LOGIC DEVICES AND FPGA 9 Hrs.
Basic Concepts; Programming Technologies; Programmable Read Only Memory (PROM), Programmable Logic Array
(PLA), Programmable Array Logic (PAL), Structure of standard PLD’s; Complex PLD’s (CPLD); System Design using PLD’s;
Design of Combinational and Sequential Circuits using PLD’s; Introduction to Field Programmable Gate Arrays; Virtex FPGA
Architecture – Virtex families of FPGA – Virtex 5 ( or later version) in detail
Max. 45 Hrs.

COURSE OUTCOMES
On completion of the course, student will be able to
CO1 - Realize the functionalities of combinational and sequential logic circuits.
CO2 - Design and model the CSSN and to analyze it.
CO3 - Design and model the ASN and to analyze it.
CO4 - Use the ASM chart for designing the sequential networks.
CO5 - Program the different types of PLDs
CO6 - Appraise about different vertex FPGA families.

TEXT / REFERENCE BOOKS
1. Donald G.Givone, Digital principles and Design, Tata McGraw Hill, 2nd Edition, reprint, 2012.
2. John MYarbrough, Digital Logic applications and Design, Thomson Learning, 2010 reprint.
3. Charles H. Roth, Jr. and Larry L. Kinney, "Fundamentals of Logic Design", 6th Edition, Cengage Learning, 2012.
4. Richard F. Tinder, "Engineering Digital Design", 2nd Edition Revised, Academic Press, 2000, Reprint 2012.

END SEMESTER EXAMINATION QUESTION PAPER PATTERN
Max. Marks: 100 Exam Duration: 3 Hrs.
PART A: 5 Questions of 6 marks each - No choice 30 Marks
PART B: 2 Questions from each unit of internal choice, each carrying 14 marks 70 Marks
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